The present invention relates to a method for fabricating embedded dynamic-random-access memory (DRAM), more specifically, to a method for fabricating embedded DRAM with a logic cell structure having salicide contacts.
As in the prior art, it is usually to use a salicide block mask layer to remain silicon oxide atop the memory cell region and then form salicide only on the periphery logic region in the embedded DRAM process, as shown in FIG. 1. Before forming salicide on the periphery logic region, it is necessary to remove silicon oxide layer atop the periphery logic region by wet dip, which increases the difficulty of controlling oxide loss in the STI or LOCOS field oxide.
Referring to FIG. 1, it demonstrates a cross-sectional view of an embedded DRAM structure with a logic cell and a memory cell. Besides, the logic cell of the embedded DRAM structure has salicide contact on the source/drain regions and the gate structures. A substrate 100 is provided for the base of the embedded DRAM structure and shallow-trench-isolation region 110 are formed in the substrate 100 to define a PMOS region 10, an NMOS region 20 and a memory cell region 30. A gate oxide layer 120 is formed on the PMOS region 10, the NMOS region 20 and the memory cell region 30. A gate structure 121 and a gate structure 122 are respectively formed on the gate oxide layer 120 on the PMOS region 10 and the NMOS region 20. The PMOS region 10 has source/drain regions 161 of a PMOS device in the substrate 100 and the NMOS region has source/drain region 162 of an NMOS device in the substrate 100. A salicide layer 150 is formed on the source/drain regions 161, 162, the gate structures 121 and 122. Furthermore, the gate structure 121 and the gate structure 122 are protected by spacers 130.
On the memory cell region 30, a stack structure consisting of a layer 123, a layer 124 and a layer 125 is formed on the gate oxide layer 120. The stack structure is indicated as the gate structure of the memory cells on the memory cell region 30. The stack structure is surrounded by the spacers 130, which is formed of silicon oxide or silicon nitride material. A silicon oxide layer 140 covers on the gate structure on the memory cell region 30 to serve as a protecting layer of the gate structure. The memory cell on the memory cell region 30 has source/drain regions 163 formed in the substrate 100.
For simultaneously fabricating the logic cells with salicide contacts and the memory cell on a substrate, a silicon oxide layer 140 covers on the memory cell region to protect the memory cells during the self-aligned silicide (salicide) process of the logic cells in the embedded DRAM. Before the salicide process is performed on the logic cells, the silicon oxide layer 140, as shown in FIG. 1, must be removed in the periphery logic region by wet dip.
As the silicon oxide layer 140 on the region 10 and 20 is stripped by wet etching techniques, the silicon oxide material in the shallow-trench-isolation region 110 could be etched and the isolation effect of the STI region 110 would be reduced because of the silicon oxide loss in the STI region 110. Alternatively, if the memory cell region is not protected by covering a silicon oxide layer, metal silicide layers will be formed on the memory cell region. The memory cells with silicide layers covering thereon would have not a good operating characteristics.
Therefore, a method for fabricating an embedded DRAM on a substrate is needed and the memory cells of the embedded DRAM must be protected by a protective layer during the salicide process of the logic cells in the device.
The present invention discloses a method to fabricate embedded DRAM with salicide logic cells and memory cells. A substrate is provided and isolation regions are formed thereon to define a logic cell region and a memory cell region. Besides, a gate structure is formed on the memory cell region. Light-doped-drain (LDD) regions of the logic cells are formed in the substrate adjacent to the gate structure. A silicon nitride layer is formed on the substrate and the gate structure. The silicon nitride layer is etched to expose the substrate in the logic cell region. An ion implantation process is performed to form source/drain regions of the logic cell region. Finally, a salicide process is performed to form a salicide layer on the source/drain regions of the logic cell region, wherein the gate structure of the memory cell region is protected by the silicon nitride layer during the salicide process.